1. Field of the Invention
The present invention relates to a data flow graph processing method for processing a data flow graph necessary to configure the operation of a reconfigurable circuit with modifiable functions and a processing apparatus provided with a reconfigurable circuit with modifiable functions.
2. Description of the Related Art
Recently, efforts have been made toward the development of are configurable processor using a multifunctional element called arithmetic logic unit which is provided with a plurality of basic operating functions (see, for example, patent document No. 1). In a reconfigurable processor, command data are sequentially set in an ALU so that a target circuit for processing an operation is achieved through the entire sequence.
Command data is generated as data for mapping a data flow graph (DFG) into an ALU circuit, the DFG being a data flow generated from a source program described in a high-level language such as C. Command data is generated according to the order of processing in the circuit formed on the ALU circuit and is stored at consecutive addresses in a storage area.
Related Art List
JP 2004-220377 A
In the related-art reconfigurable processor, command data is sequentially read from a memory and supplied to an ALU circuit to configure the function of the ALU circuit. Therefore, if condition-handling such as an if statement is located in a source program, it is necessary to set command data for executing a plurality of branching processes on an ALU circuit so as to execute the associated operations beforehand. After the making a conditional determination, the operation result corresponding to the determination needs to be selected.
In this case, only the operation result in one of the branches is actually used and the other operation result is not used. This has resulted in causing processing time for operation to be extended beyond what is necessary.
When a loop operation such as a for statement with a predetermined loop count is located in a source program, the related-art reconfigurable circuit has to store, at consecutive addresses in a memory, a command data group for the same loop operation a predetermined number of times, the number of times of storage being equal to the loop count in the same loop operation.
For example, when the loop count is 10, the same command data group should be stored 10 times in a memory, thereby increasing the volume of command data. When the loop count is indefinite, the number of repetition is unknown so that it is difficult to generate command data itself.
The present invention has been made in view of the aforementioned points and relates to a data flow graph processing method capable of efficiently processing a data flow graph necessary to configure the operation of a reconfigurable circuit. The present invention also relates to a processing apparatus provided with a circuit reconfiguration function capable of executing operations efficiently.